Example embodiments of the inventive concepts relate to a digital phase-locked loop (DPLL). For example, at least some example embodiments relate to a DPLL having improved signal characteristics and/or a method of operating the same.
A phase-locked loop (PLL) may be a control circuit configured to generate an output clock signal having a phase related to a phase of an input clock signal. The output clock signal generated by the PLL may be a system clock signal used for various digital products. A digital PLL (DPLL) that is based on digital control may be used as an example of the PLL. Performance of the DPLL may be degraded due to a noise of the output signal.